1. Field of the Invention
The present invention is generally directed to semiconductor processing, and, more particularly, to a method of removing a layer of photoresist using a polishing tool.
2. Description of the Related Art
A conventional integrated circuit device, such as a microprocessor, is typically comprised of many thousands of semiconductor devices, e.g., transistors, formed above the surface of a semiconducting substrate. For the integrated circuit device to function, the transistors must be electrically connected to one another through conductive interconnections.
Many modern integrated circuit devices are very densely packed, i.e., there is very little space between the transistors formed above the substrate. Thus, these conductive inter-connections must be made in multiple layers to conserve plot space on the semiconducting substrate. This is typically accomplished through the formation of a plurality of conductive lines and conductive plugs formed in alternative layers of dielectric materials formed on the device. The conductive plugs are means by which various layers of conductive lines, and/or semiconductor devices, may be electrically coupled to one another. This interconnected network of contacts and lines allows electrical signals to propagate throughout the integrated circuit device. The conductive lines and plugs may be made of a variety of conductive materials, such as copper, aluminum, aluminum alloys, titanium, tantalum, titanium nitride, tantalum nitride, tungsten, etc. These conductive lines and plugs may be formed by a variety of known techniques, e.g., single damascene processing, dual damascene processing, etc.
The openings in the layer of dielectric material for the conductive interconnections may be formed by performing known photolithography and etching process. In general, photolithography is a process in which a layer of photoresist, a material whose structure may be changed upon exposure to a light source, is formed above a layer of dielectric material in which it is desired to form openings for a conductive interconnection, e.g., a line or plug. Essentially, the image that is desired to ultimately be formed in the underlying process layer will first be formed in the layer of photoresist by exposing portions of the photoresist layer to an appropriate light source. Following development of the photoresist layer, the portions of the photoresist layer exposed to the light source will be resistant to subsequent etching processes to be performed on the semiconductor device. The desired features of the semiconductor device are then formed in the underlying layer by performing one or more wet or dry etching processes to remove the portions of underlying dielectric layer that are not protected by the patterned layer of photoresist.
As these conductive interconnections have become more densely packed together, the capacitance that may exist between adjacent conductive interconnections has also become an important consideration. Increased capacitance between adjacent conductors is undesirable because it may delay signal propagation along the conductors, and it may result in increased power consumption by an integrated circuit device, as this capacitance must be charged-up during each operating cycle. As the capacitance of two conductors is inversely proportional to the distance between the conductors, reducing the device dimensions inevitably leads to an increase of the stray capacitance of adjacent conductors.
In an effort to reduce the capacitance between adjacent conductive interconnections, the dielectric materials in which the conductive interconnections will be formed have been made from materials having relatively low dielectric constants ("k"). However, care must be taken when using such materials because such low-k materials may not be stable enough to withstand subsequent processing, e.g., wet etching processes, ashing processes, etc. In particular, removing the layer of photoresist after the openings for the conductive inter-connections have been formed in the layer of dielectric material may be problematic given the nature and instability of the low-k dielectric materials used in modem device fabrication. For example, ashing processes used to remove the layer of photoresist may also damage the layer of dielectric material.
The present invention is directed to overcoming, or at least reducing the effects of, one or more of the problems set forth above.